1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to encoding and/or decoding of signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs one or more types of iterative error correction codes that oftentimes employ some form of FEC (Forward Error Correction) coding. Communications systems with iterative codes/FEC are often able to achieve lower bit error rates (BER), clock error rates (BLER), or some other measure of error rate than alternative means for a given signal to noise ratio (SNR).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
FEC encoding generally encodes information bits and generates parity bits (sometimes alternatively referred to as redundancy bits). In some instances, these parity bits are interspersed among the information bits when generating a codeword. A common prior art approach is to intersperse the parity bits evenly throughout the codeword using real time calculations based on the size of the number of information bits, the number of parity bits, etc. This inherently involves the need to calculate the spacing of the parity bits within the to be generated codeword on a cycle to cycle basis. Also, in an attempt to perform this even distribution within a discrete system, it is typical that the spacing is non-uniform (e.g., x number of information bits reside between a first parity bit and a second parity bit, and x+n number of information bits reside between the second parity bit and a third parity bit, where x and n are integers, where each of these n may as small as 1).
FIG. 6 illustrates a prior art embodiment 600 showing even interspersing of parity bits among information bits within a codeword on a cycle by cycle basis. In this prior art embodiment 600, the information bits include K=46 bits, and the parity bits include (N−K)=P=8 parity bits of a total number of available bits on N=54.
As can be seen, the parity bits are being evenly distributed among the total number of bits. Five information bits (e.g., bits 0, 1, 2, 3, 4) are placed during a cycle 0 before placing a first parity bit (e.g., bit 46) and then six information bits (e.g., bits 5, 6, 7, 8, 9, 10) are placed after the first parity bit (e.g., bit 46).
Then, in a cycle 1, a second parity bit (e.g., bit 47) is placed initially followed by six information bits (e.g., bits 11, 12, 13, 14, 15, 16) which is then followed by a third parity bit (e.g., bit 48). As can be seen already, there is a different number of information bits placed between each of the first, second and third parity bits (e.g., 5, 6, and 6, respectively).
This also inherently includes additional complexity on an apparatus performing such distribution of parity bits among the information bits. If the data to be processed in this manner, if the data comes in at a fixed rate, then it is imperative to decide which of the data are information bits and which are parity bits on a cycle to cycle basis. Each input of such a prior art scheme must be routed to both storage for the front portion (e.g., information bit portion) and storage for the back portion (e.g., parity bit portion) for proper generation of the codeword.
Generally speaking, this prior art approach of attempting to distribute the parity bits evenly among the information bits introduces complexity in a hardware implementation, in that, the parity bits will move around to different locations among the information bits when performing such processing of signals including different numbers of information bits and different numbers of parity bits.